The invention relates to the fabrication of vertically constructed planar transistors in a monolithic semiconductor substrate wherein high precision of the photolithographic masking operations is not required to have perfect alignment. The process is self-aligning. While the process can easily be applied in the fabrication of discrete transistors its main benefit is realized in the fabrication of IC devices that incorporate vertical PNP and NPN transistors that can be simultaneously fabricated into a silicon wafer using the well-known planar, PN junction isolation, monolithic IC structure.
U.S. Pat. No. 4,940,671, issued on Jul. 10, 1990, to J. Barry Small and Matthew S. Buynoski. It relates to an IC structure in which substantially conventional high performance NPN transistors are fabricated simultaneously with vertical high performance PNP transistors. Both transistor types can be independently optimized to provide high electrical performance and the process produces PNP and NPN devices that are substantially matched and complementary. U.S. Pat. No. 4,910,160, issued on Mar. 20, 1990, to Dean C. Jennings and Matthew S. Buynoski, It also relates to the process disclosed in U.S. Pat. No. 4,940,671, but sets forth improvements related to power transistor construction.
These two patents are assigned to the assignee of the present invention and their teachings are incorporated herein by reference. The processes disclosed in the two patents have been employed to produce an IC product line known by the trademark VIP.TM. process IC devices. VIP is developed as an acronym for vertically integrated PNP. This development is significant because the standard IC devices previously employed, either lateral PNP transistors or substrate collector PNP transistors, both of which displayed undesirable characteristics. The prior art lateral transistors typically had low current gain performance and limited frequency response. The substrate collector devices had good current gain, but could not be electrically isolated and operated independently.
The invention relates to a process that employs self alignment in the photolithographic processes. While it could be employed in other planar process applications, including discrete devices, its main interest lies in its use in the fabrication of VIP process IC devices.